Technical Field
The present disclosure relates generally to wireless communication systems, and more specifically, to methods and devices for reducing noise within a phased-locked loop (PLL).
Background
Phase locked loops (PLLs) are commonly used in telecommunications, computers and other electronics that utilize a precise clock for coordinating and synchronizing activities. PLLs can provide a local oscillator (LO) function in a radio receiver or transmitter. PLLs are also used for clock-signal distribution and noise reduction, as well as the clock source for high-sampling-rate analog-to-digital or digital-to-analog conversion.
A phase locked loop (PLL) forces an oscillator (e.g., voltage controlled oscillator (VCO) or digitally controlled oscillator (DCO)) to replicate or track a reference frequency and phase at an input when the PLL is in a lock configuration. When locked, the frequencies of the input (e.g., at a phase detector) and output (e.g., at a VCO) are tracked exactly (e.g., input frequency=output frequency). The VCO is often the main contributor to PLL noise due to degradation from source voltage noise. The overall power supply noise rejection (PSNR) of a PLL is a bandpass transfer function, and its center frequency is close to a PLL bandwidth.
As noise performance of PLLs improves, the impact of power supply noise is becoming increasingly evident, and may even limit noise performance in some cases. Accordingly, reducing noise within PLLs is desirable.